1. Field of the Invention
The present invention relates to a method and apparatus for decoding an image having a format for a digital video camera so called a digital camcorder (DV), that can minimize the memory capacity required for implementing a variable-length decoder and the operation time for searching blocks when decoding bit streams encoded in a format for the digital camcorder (DV).
2. Background of the Related Art
Recently, the use of a digital image has been expanded. Especially, a moving image is generally stored and transmitted after being compressed and encoded since lots of resources are required for storing and transmitting the moving image. As the standard widely used for this purpose, there exist an MPEG (moving picture experts group)-1 and an MPEG-2 based on a discrete cosine transform (DCT) and motion estimation and compensation technique, which are actively applied to a video compact disc (CD), a digital versatile disc (DVD), a digital television, etc. Currently, they are substituted for the existing analog video reproducing appliances for home use, while a digital camcorder (DV) is substituted for a camcorder that is the existing analog recording and reproducing appliance.
The digital camcorder requires an encoder having the complicated standard of an MPEG series, and this causes the application of such an encoder to be limited to broadcasting appliances. Also, the digital camcorder is designed to have a different construction from the MPEG considering the characteristics in that both an encoder and a decoder should be included in the camcorder. Especially, since a motion estimation and compensation section generally used in the standard of the MPEG and so on requires a high-order operation amount, it is difficult to mount the motion estimation and compensation section onto a general home appliance. This causes the compression and encoding standard of a simple structure that does not perform the motion estimation and compensation to be proposed.
This encoding standard for the digital camcorder is disclosed in “IEC 61834-2 Recording—Helical-scan digital video cassette recording system using 6.35 mm magnetic tape for consumer use (525-60, 625-50, 1125-60, and 1250-50 systems)—Part 2: SD format for 525-60 and 625-50 systems.” This standard is generally called a DV format.
As the use of the digital camcorder adopting the DV format is spreading, there has been an increasing demand for an additional function for processing data of the DV format in a home video appliance such as a digital television receiver as well as the function of the digital camcorder itself.
According to the DV format, the whole image is divided into two types of macro blocks as shown in FIGS. 1 and 2. The 525-60 system uses either of the two types of macro blocks in accordance with the position in the image, while 626-50 system uses only the type of macro blocks in FIG. 2. As is common to the two types of macro blocks, DCT blocks DCT0˜DCT5 for four luminance signals Y0, Y1, Y2, and Y3 and two chrominance signals CR and CB are sequentially encoded as shown in FIG. 3. The respective DCT block is a unit block for performing the DCT, and is composed of 8*8 pixels. At this time, in distinction from the compression and encoding standard of the MPEG series, a fixed bit amount is allocated to each video segment in the DV format for the strict management thereof.
That is, as shown in FIG. 4, one video segment is composed of 5 macro blocks. Thus, 30 DCT blocks constitute one video segment.
Also, since a trick-mode reproducing function is important according to the characteristic of the camcorder, a DC coefficient of the respective block is written in a fixed position for a high-speed forward/reverse reproduction. At this time, AC coefficients are sequentially stored in the remaining places except for the place where the DC coefficient is written.
A general encoding process for storing the AC coefficients is performed as follows.
(a) The bit stream obtained as a result of compression and encoding of the respective DCT blocks is sequentially written in a basic area allocated in the respective DCT block. The basic area allocates 14 bytes to a luminance-component block, and 10 bytes to a chrominance-component block. At this time, if the bit stream exceeds the allocated basic area, the encoding of the corresponding DCT block is stopped, and the next DCT block is processed.
(b) The step (a) is performed with respect to 30 DCT blocks.
(c) The processing of the DCT block stopped at the step (a) in the respective macro block continues. That is, the excess portion of the DCT block that exceeds the basic area at the step (a) is stored in a surplus portion of the basic area allocated to another DCT block whose encoding is completed.
(d) The step (c) is repeatedly performed with respect to 5 macro blocks until the excess portion or the surplus portion in the respective macro block vanishes completely. As a result, one part of the 5 macro blocks which constitute the video segment has the surplus portion, and the other part has the excess portion.
(e) The excess portion of the macro block that exceeds the basic area is stored in the surplus portion of the basic area allocated to another macro block. Here, the basic area allocated to the macro block means the sum of basic areas allocated to the DCT blocks included in the respective macro block.
(f) The step (e) is repeatedly performed with respect to the whole region of the video segment until the excess portion or the surplus portion vanishes completely.
The decoding of the bit streams encoded as described above is generally performed according to the following order.
(a) The variable-length decoding is sequentially performed with respect to the DCT blocks in the respective macro block. The decoded data is sequentially stored in a storage device. At this time, if an end of block (EOB) of the DCT block is not transmitted at a time point when all the data of the basic area allocated to the corresponding DCT block is decoded, the decoding of the corresponding DCT block is stopped, and the next DCT block is decoded.
(b) The step (a) is performed with respect to 30 DCT blocks.
(c) The decoding of the DCT block in the macro block, of which the EOB is not transmitted, i.e., the DCT block that is judged to exceed the basic area allocated at the step (a), continues through the readout of the bit stream from the surplus portion of the basic area allocated to the DCT block of which the EOB is transmitted, i.e., the DCT block whose decoding is completed.
(d) The step (c) is continuously performed until the surplus portion or the excess portion in the macro block vanishes completely.
(e) The decoding of the 6 DCT blocks in the macro block whose decoding is not completed continues through the readout of the bit stream from the surplus portion of the basic area allocated to the macro block in which the decoding of the 6 DCT blocks is completed.
(f) The step (e) is repeatedly performed until the decoding of all the macro blocks is completed. In a normal condition, the completion of decoding of the video segment means that the EOBs of the 30 DCT blocks are detected.
Conventionally, the complicated process as described above is performed for the decoding of the video segment, and this causes the design of the storage device and control logic circuit to exert an important effect upon the cost and performance of the system.
Specifically, since the decoding process is performed in the unit of a video segment, a storage device for storing a bit stream for one video segment is basically required, and its size should be of (14*4+10*2)*8*5=3,040 bits as defined in the standard. In practice, a double buffer is used for the real-time process, and thus two storage devices are necessary.
The capacity of the storage device required for the following process is determined according to the implementation method of the variable-length decoder. At this time, in case of implementing the variable-length decoder according to the above method, a storage device for storing DCT coefficients for two video segments, i.e., 60 DCT blocks, is required for the real-time process since an inverse DCT (IDCT) can be performed after the variable-length decoding is completed in all.
Since 64 DCT coefficients are included in one DCT block, the capacity of the storage device will be of 30,720 bits. Also, since the decoding process should be repeatedly performed in the unit of a DCT block, a macro block, and a video segment, a temporary storage device for storing the bit stream obtained as a result of performing the respective steps also requires the size of one video segment, which is the same size as the storage device for storing the input bit stream, i.e., 3,080 bits.
Also, in case of the DCT block that exceeds the allocated basic area, the bit stream of another DCT block whose decoding is completed should be searched in order to read out its own bit stream stored in the surplus space of another DCT block. This requires a long operation time.